Vlsi Implementation and Performance Analysis of Efficient Mixed-radix 8-2 Fft Algorithm with Bit Reversal for the Output Sequences

In recent years, as a result of advancing VLSI technology, OFDM has received a great deal of attention and been adopted in many new generation wideband data communication systems such as IEEE 802.11a, HiPerLAN/2,digital audio/video broadcasting (DAB/DVB-T) and asymmetric digital subscriber line (ADSL), very high speed digital subscriber line (VDSL) in wireless and wired communications, respectively. In these communication systems the different applications mentioned above have different demands in operation speed and length of FFT/IFFT. The modified Mixed Radix 8-2 Butterfly FFT with bit reversal for the output sequence derived by index decomposition technique is our proposed VLSI system architecture to design the prototype FFT/IFFT processor for OFDM systems. In this paper the analysis of several FFT algorithms such as radix-2, radix-4, split radix and mixed radix 42 and proposed mixed radix8-2 were designed using VHDL and outputs are analysed. Mainly the results show that the proposed processor architecture can save the area approximately 5% and power more than 40% when compared to basic radix 2 system, which may be attractive for many real-time systems. Reduction in area and power can further leads to less implementation cost. Also the proposed algorithm makes an offer the simple bit reversal mechanism which is only supported by a fixed radix FFT algorithm.